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hcpl-540x*, 5962-89570, hcpl-543x, hcpl-643x, 5962-89571 hermetically sealed, very high speed, logic gate optocouplers data sheet *see matrix for available extensions. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. features ? dual marked with device part number and dla standard microcircuit drawing ? manufactured and tested on a mil-prf-38534 certifi ed line ? qml-38534, class h and k ? three hermetically sealed package confi gurations ? performance guaranteed over full military temperature range: -55 c to +125 c ? high speed: 40 m bit/s ? high common mode rejection 500 v/ ? s guaranteed ? 1500 vdc withstand test voltage ? active (totem pole) outputs ? three stage output available ? high radiation immunity ? hcpl-2400/30 function compatibility ? reliability data ? compatible with ttl, sttl, lsttl, and hcmos logic families applications ? military and space ? high reliability systems ? transportation, medical, and life critical systems ? isolation of high speed logic systems ? computer-peripheral interfaces ? switching power supplies ? isolated bus driver (networking applications) C (5400/1/k only) ? pulse transformer replacement ? ground loop elimination ? harsh industrial environments ? high speed disk drive i/o ? digital isolation for a/d, d/a conversion truth tables (positive logic) multichannel devices input output on (h) l off (l) h single channel dip input enable output on (h) l l off (l) l h on (h) h z off (l) h z the connection of a 0.1 ? f bypass capacitor between v cc and gnd is recommended. description these units are single and dual channel, hermetically sealed optocouplers. the products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full mil-prf-38534 class level h or k testing or from the appro priate dla drawing. all devices are man- ufactured and tested on a mil-prf-38534 certifi ed line and are included in the dla qualifi ed manufac turers list, qml-38534 for hybrid microcircuits. functional diagram multiple channel devices available v cc v o v e gnd
2 selection guideCpackage styles and lead confi guration options package 8 pin dip 8 pin dip 20 pad lccc lead style through hole through hole surface mount channels 1 2 2 common channel wiring none v cc , gnd none avago part # & options commercial hcpl-5400 hcpl-5430 hcpl-6430 mil-prf-38534, class h hcpl-5401 hcpl-5431 hcpl-6431 mil-prf-38534, class k HCPL-540K hcpl-543k hcpl-643k standard lead finish gold plate gold plate solder pads* solder dipped* option 200 option 200 butt cut/gold plate option 100 option 100 gull wing/soldered* option 300 option 300 class h smd part # prescript for all below 5962- 5962- 5962- gold plate 8957001pc 8957101pc solder dipped* 8957001pa 8957101pa 89571022a butt cut/gold plate 8957001yc 8957101yc butt cut/soldered* 8957001ya 8957101ya gull wing/soldered* 8957001xa 8957101xa class k smd part # prescript for all below 5962- 5962- 5962- gold plate 8957002kpc 8957103kpc solder dipped* 8957002kpa 8957103kpa 8957104k2a butt cut/gold plate 8957002kyc 8957103kyc butt cut/soldered* 8957002kya 8957103kya gull wing/soldered* 8957002kxa 8957103kxa *solder contains lead. each channel contains an algaas light emitting diode which is optically coupled to an integrated high gain photon detector. this combination results in very high data rate capability. the detector has a threshold with hysteresis, which typically provides 0.25 ma of diff eren- tial mode noise immunity and minimizes the poten tial for output signal chatter. the detector in the single channel units has a three state output stage which eliminates the need for a pull-up resistor and allows for direct drive of a data bus. all units are compatible with ttl, sttl, lsttl, and hcmos logic families. the 35 ns pulse width distortion speci- fi cation guaran tees a 10 mbd signaling rate at +125 c with 35% pulse width distortion. figures 13 through 16 show recommended circuits for reducing pulse width distortion and optimizing the signal rate of the product. package styles for these parts are 8 pin dip through hole (case outlines p), and leadless ceramic chip carrier (case outline 2). devices may be purchased with a variety of lead bend and plating options. see selection guide table for details. standard microcircuit drawing (smd) parts are available for each package and lead style. because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifi cations, and per- formance characteristics shown in the fi gures are similar for all parts. occasional exceptions exist due to package variations and limita tions and are as noted. addition ally, the same package assembly processes and materials are used in all devices. these similarities give justifi cation for the use of data obtained from one part to represent other parts per form ance for die related reliability and certain limited radiation test results.
3 functional diagrams 8 pin dip 8 pin dip 20 pad lccc through hole through hole surface mount 1 channel 2 channels 2 channels note: all dip devices have common v cc and ground. lccc (leadless ceramic chip carrier) package has isolated channels with separate v cc and ground connections. outline drawings 20 terminal lccc surface mount, 2 channels 8 pin dip through hole, 1 and 2 channel 7 5 6 8 1 2 3 4 v cc gnd v e v o v cc 7 5 6 8 v o1 gnd 1 2 3 4 v o2 gnd 1 v o2 v o1 19 20 2 3 8 7 v cc2 v cc1 10 gnd 2 15 13 12 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 plcs) 4.95 (0.195) 5.21 (0.205) 8.70 (0.342) 9.10 (0.358) 1.78 (0.070) 2.03 (0.080) 0.51 (0.020) 0.64 (0.025) (20 plcs) 1.52 (0.060) 2.03 (0.080) metallized castillations (20 plcs) 2.16 (0.085) terminal 1 identifier note: dimensions in millimeters (inches). solder thickness 0.127 (0.005) max. 1.14 (0.045) 1.40 (0.055) 3.81 (0.150) min. 4.32 (0.170) max. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) note: dimensions in millimeters (inches).
4 leadless device marking leaded device marking compliance indicator,* date code, suffix (if needed) avago qyywwz xxxxxx xxxxxxx xxx usa * 50434 country of mfr. avago fscn* avago logo dla smd* pin one/ esd ident avago p/n dla smd* * qualified parts only compliance indicator,* date code, suffix (if needed) avago qyywwz xxxxxx * xxxx xxxxxx usa 50434 dla smd* avago fscn* avago logo country of mfr. avago p/n pin one/ esd ident dla smd* * qualified parts only hermetic optocoupler options option description 100 surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. this option is available on commercial and hi-rel product in 8 pin dip (see drawings below for details). 200 lead fi nish is solder dipped rather than gold plated. this option is available on commercial and hi-rel product in 8 pin dip. dla drawing part numbers contain provisions for leadfi nish. all leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. 300 surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. this option is available on commercial and hi-rel product in 8 pin dip (see drawings below for details). this option has solder dipped leads. *solder contains lead. 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 0.51 (0.020) min. 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5 max. 4.57 (0.180) max. 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 1.07 (0.042) 1.32 (0.052)
5 absolute maximum ratings no derating required up to +125 c. parameter symbol min. max. units note storage temperature t s -65 +150 c operating temperature t a -55 +125 c case temperature t c +170 c junction temperature t j +175 c lead solder temperature 260 for 10 sec c average forward current (each channel) i f(avg) 10 ma peak input current (each channel) i f(peak) 20 ma 1 reverse input voltage (each channel) v r 3v supply voltage v cc 0.0 7.0 v average output current (each channel) i o(avg) -25 25 ma output voltage (each channel) v o -0.5 10 v output power dissipation (each channel) p o 130 mw package power dissipation (each channel) p d 200 mw note: enable pin 7. an external 0.01 ? f to 0.1 f bypass capacitor must be connected between v cc and ground for each package type. esd classifi cation (mil-std-883, method 3015) hcpl-5400/01/0k ( ), class 2 hcpl-5430/31/3k and hcpl-6430/31/3k (dot), class 3 8 pin ceramic dip single channel schematic 2 + C v f v cc 8 v e 7 v o 6 gnd 5 i cc i e i f anode cathode 3 recommended operating conditions parameter symbol min. max. units input current (high) i f(on) 610ma supply voltage, output v cc 4.75 5.25 v input voltage (low) v f(off) C 0.7 v fan out (each channel) n C 5 ttl loads single channel product only three state enable voltage v e -0.5 10 v single channel product only high level enable voltage v eh 2.0 v cc v low level enable voltage v el 0 0.8 v
6 electrical characteristics t a = -55 c to +125 c, 4.75 v v cc 5.25 v, 6 ma i f(on) 10 ma, 0 v v f(off) 0.7 v, unless otherwise specifi ed. parameter sym. test conditions subgroups group a 10 limits fig. notes min. typ.* max. units low level output voltage v ol i ol = 8.0 ma (5 ttl loads) 1, 2, 3 0.3 0.5 v 1 9 high level output voltage v oh i oh = -4.0 ma 1, 2, 3 2.4 v 2 9 output leakage current i ohh v o = 5.25 v, v f = 0.7 v 1, 2, 3 100 ? a 9 logic high supply current single channel i cch v cc = 5.25 v, v e = 0 v 1, 2, 3 17 26 ma dual channel 34 52 13 logic low supply current single channel i ccl 1, 2, 3 19 26 ma dual channel 38 52 13 input forward voltage v f i f = 10 ma 1, 2, 3 1.0 1.35 1.85 v 4 9 input reverse breakdown voltage v r i r = 10 ? a 1, 2, 3 3.0 4.8 v 9 input-output insulation leakage current i i-o v i-o = 1500 vdc, rh 65%, t = 5 s 1 1.0 ? a 2, 3 propagation delay time logic low output t phl 9, 10, 11 33 60 ns 5, 6, 7 4, 9 propagation delay time logic high output t plh 9, 10, 11 30 60 ns 5, 6, 7 4, 9 pulse width distortion pwd 9, 10, 11 3 35 ns 5, 6, 7 4, 9 logic high common mode transient immunity |cm h |v cm = 50 v p-p , i f = 0 ma 9, 10, 11 500 3000 v/ ? s 11 5, 9, 11 logic low common mode transient immunity |cm l |v cm = 50 v p-p , i f = 6 ma 9, 10, 11 500 3000 v/ ? s 11 5, 9, 11 single channel product only parameter sym. test conditions subgroups group a10 limits fig. notes min. typ.* max. units logic high enable voltage v eh 1, 2, 3 2.0 v logic low enable voltage v el 1, 2, 3 0.8 v logic high enable current i eh v e = 2.4 v 1, 2, 3 20 ? a v e = 5.25 v 1, 2, 3 100 logic low enable current i el v e = 0.4 v 1, 2, 3 -0.28 -0.4 ma high impedance state supply current i ccz v cc = 5.25 v, v e = 5.25 v 1, 2, 3 22 28 ma high impedance state output current i ozl v o = 0.4 v, v e = 2 v 1, 2, 3 -20 ? a i ozh v o = 2.4 v, v e = 2 v 20 v o = 5.25 v, v e = 2 v 100 *all typical values are at v cc = 5 v, t a = 25 c, i f = 8 ma except where noted.
7 notes: 1. not to exceed 5% duty factor, not to exceed 50 ? sec pulse width. 2. all devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 3. this is a momentary withstand test, not an operating condition. 4. t phl propagation delay is measured from the 50% point on the rising edge of the input current pulse to the 1.5 v point on the falling edge of the output pulse. the t plh propagation delay is measured from the 50% point on the falling edge of the input current pulse to the 1.5 v point on the rising edge of the output pulse. pulse width distortion, pwd = |t phl - t plh |. 5. cm l is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state (v o(max) < 0.8 v). cm h is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state (v o(min) > 2.0 v). 6. duration of output short circuit time not to exceed 10 ms. 7. power supply noise immunity is the peak to peak amplitude of the ac ripple voltage on the v cc line that the device will withstand and still remain in the desired logic state. for desired logic high state, v oh(min) > 2.0 v, and for desired logic low state, v ol(max) < 0.8 v. 8. measured between adjacent input pairs shorted together for each multichannel device. 9. each channel. 10. standard parts receive 100% testing at 25 c (subgroups 1 and 9). smd, class h and class k parts receive 100% testing at 25 c, 125 c, and -55 c (subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 11. parameters are tested as part of device initial characterization and after design and process changes. parameters are guaranteed to limits specifi ed for all lots not specifi cally tested. 12. propagation delay skew is defi ned as the diff erence between the minimum and maximum propagation delays for any given group of optocouplers with the same part number that are all switching at the same time under the same operating conditions. 13. the hcpl-6430, hcpl-6431, and hcpl-643k dual channel parts function as two independent single channel units. use the single channel parameter limits. typical characteristics all typical values are at t a = 25c, v cc = 5 v, i f = 8 ma, unless otherwise specifi ed. parameter symbol typ. units test conditions fig. notes input current hysteresis i hys 0.25 ma v cc = 5 v 3 input diode temperature coeffi cient ? v f ? t a -1.11 mv/c i f = 10 ma 4 resistance (input-output) r i-o 10 12 ? v i-o = 500 v 2 capacitance (input-output) c i-o 0.6 pf f = 1 mhz, v i-o = 0 v 2 logic low short circuit output current i osl 65 ma v o = v cc = 5.25 v, i f = 10 ma 6, 9 logic high short circuit output current i osh -50 ma v cc = 5.25 v, i f = 0 ma, v o = gnd 6, 9 output rise time (10-90%) t r 15 ns 5 output fall time (90-10%) t f 10 ns 5 propagation delay skew t psk 30 ns 10 12 power supply noise immunity psni 0.5 v p-p 48 hz f ac 50 mhz 7 single channel product only parameter symbol typ. units test conditions fig. notes input capacitance c in 15 pf f = 1 mhz, v f = 0 v, pins 2 and 3 output enable time to logic high t pzh 15 ns 8, 9 output enable time to logic low t pzl 30 ns 8, 9 output disable time from logic high t phz 20 ns 8, 9 output disable time from logic low t plz 15 ns 8, 9 dual and quad channel product only input capacitance c in 15 pf f = 1 mhz, v o = 0 v input-input leakage current i i-i 0.5 na rh 65%, v i-i = 500 vdc 8 input-input resistance r i-i 10 12 ? v i-i = 500 v 8 input-input capacitance c i-i 1.3 pf f = 1 mhz, v f = 0 v 8
8 figure 1. typical logic low output voltage vs. logic low output current figure 2. typical logic high output voltage vs. logic hi gh output current figure 3. typical output voltage vs. input forward current figure 4. typical diode input forward current characteristic
9 gnd v cc i f 5.0 v d.u.t. 1.3 k pulse generator z o = 50 t r = t f = 5 ns c1 30 pf input v e monitoring node v cc d 1 d 2 2.5 k d 3 d 4 s2 s1 v o 8 7 6 5 1 2 3 4 0.1 ? figure 8. test circuit for t phz , t pzh , t plz , and t pzl . (single channel product only) figure 5. test circuit for t plh , t phl , t r , and t f figure 6. typical propagation delay vs. ambient temperature figur e 7. typical propagation delay vs. input forward current gnd v cc i f 5.0 v d.u.t. 1.3 k input monitoring node pulse gen. t r = t f = 5 ns f = 500 khz 25 % duty cycle 30 pf c2 the probe and jig capacitances are represented by c 1 and c 2 . all diodes are 1n4150 or equivalent. v o output monitoring node v cc 2.5 k c1 15 pf 100 0.1 f
10 figure 9. typical enable propagation delay vs. ambient temperature. (single channel product only) figure 11. test diagram for common mode transient immunity and typical waveforms figure 10. propagation delay skew, t psk , waveform figure 12. operating circuit for burn-in and steady state life tests v ff gnd v cc v cm + pulse gen. b d.u.t. i f output v o monitoring node v cc = 5.0 v + c l 15 pf + a 0.1 f* gnd v cc d.u.t.* * for single channel units, ground enable pin. conditions: i f = 10 ma v cc = 5.25 v v in + i f i o = 25 ma 0.01 f t a = +125 ? 2.1 v 100 w typ. i o 100 w i cc v dc = 3.0 v
11 mil-prf-38534 class h, class k, and dla smd test program the amount of time required for a systems output to change from a logic 1 to a logic 0, when given a stimulus at the input (see figure 5). when t plh and t phl diff er in value, pulse width distortion results. pulse width distortion is defi ned as |t phl - t plh | and deter mines the maximum data rate capability of a dis- tortion-limited system. maximum pulse width distortion on the order of 25-35% is typically used when specifying the maximum data rate capabili ties of systems. the exact fi gure depends on the particular appli cation (rs-232, pcm, t-1, etc.). these high performance opto couplers off er the advan- tages of specifi ed propagation delay (t plh , t phl ), and pulse width distortion (|t plh -t phl |) over temperature and power supply voltage ranges. figure 13. recommended hcpl-5400 interface circuit applications gnd v cc hcpl-5400 226 v cc1 = +5 v ttl lsttl sttl hcmos totem pole output gate (e.g. 54as1000) data out 2 data in 1 gnd 2 y 0.1 f 274 30 pf a gnd 1 y = a v cc2 = 5 v figure 14. alternative hcpl-5400 interface circuit gnd v cc hcpl-5400 464 v cc1 = +5 v ttl lsttl sttl open collector output gate (e.g. 54s05) data out 2 data in 1 gnd 2 y 0.1 f a gnd 1 y = a v cc2 = 5 v sttl avago technologies hi-rel opto couplers are in compli- ance with mil-prf-38534 classes h and k. class h and class k devices are also in compliance with dla drawings 5962-89570, and 5962-89571. testing consists of 100% screen ing and quality confor- mance inspection to mil-prf-38534. data rate and pulse-width distortion defi nitions propagation delay is a fi gure of merit which describes the fi nite amount of time required for a system to translate in- formation from input to output when shifting logic levels. propagation delay from low to high (t plh ) specifi es the amount of time required for a systems output to change from a logic 0 to a logic 1, when given a stimulus at the input. propagation delay from high to low (t phl ) specifi es
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. obsoletes 5968-9403e av02-3838en - october 2, 2012 figure 15. recommended hcpl-5430 and hcpl-6430 interface circuit figure 16. alternative hcpl-5430 and hcpl-6430 interface circuit 2 gnd v cc hcpl-5430 226 v cc1 = 5 v totem pole output gate (e.g. 54as1000) data out y data in a 1 gnd 2 0.1 f 30 pf gnd 1 y = a v cc2 = +5 v ttl lsttl sttl hcmos data out y 226 30 pf 274 274 data in a ttl lsttl sttl hcmos gnd v cc hcpl-5430 464 v cc1 = +5 v ttl lsttl hcmos sttl sttl open collector output gate (e.g. 54as05) data out y data in a gnd 2 0.1 f gnd 1 y = a v cc2 = +5 v ttl lsttl hcmos sttl data out y data in a 464 1 2

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